PD Engineer

Skip to main contentOur CompanyOur BusinessSearch for JobsJoin Talent NetworkFAQsProfileEnglishSign InSingle PositionView All JobsPD EngineerSanta Clara, California, United States of AmericaApply NowAdd to Job CartFind out how well you match with this jobUpload your resumeJob descriptionCompany and benefitsJob ID3093898Company:Qualcomm Atheros, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs.Responsibilities: Qualcomm’s Connectivity SoC organization is seeking candidates for physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.Tasks also involve the tiles level development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals.Additional responsibilities in this role involves the experience offunctional and test (DFT) mode constraints for place and route,floorplanning, power planningIR drop analysisrouting, timing optimization and closureimplementing timing fixes and functional ECOsdebugging and fixing physical violations and formal verification.The individual also should have deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell.This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.Required Skill/experience:2+ years industry experience in the following areasTiles level or sub-system level or SoC top level physical design successful tapeout experienceFloorplanning of macro cellsPlace & Route (PNR) tool experience on Cadence Innovus and/or Synopsys Fusion CompilerTiming closure (STA) experience in Synopsys PTSIFunction ECO implementationFormal verification (FV) experiencePower domain analysis (IR Drop/PDN) experiencePhysical verification (PV) experienceMinimum Qualifications:• Bachelor's degree in Science, Engineering, or related field.Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color,...