Senior Silicon Design Engineer

You will be part of the design team driving many facets of high performance, high bandwidth Network-on-Chip designs in the start-of-the-art AI SoCs. The tasks will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different subsystems. Throughout the program you will be interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. 4+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs. 4+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure. 4+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug 4+ years of experience with Synthesis, Standard Design Constraints (SDC) and Unified Power format UPF 4+ years of experience working on SOC integration Experience with industry standard interfaces such as Advanced extensible Interface (AXI), APB, JTAG Experience with writing System Verilog assertions and coverpoints Experience with scripting languages such as Perl or Python Track record of successful tapeouts in deep sub-micron technologies Ability and willingness to adapt and work on variety of designs