Hardware Design Engineer - Graphics Silicon Implementation

## Company: Qualcomm Technologies, Inc. ## Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: Qualcomm CDMA Technologies, is the world leader in wireless ICs powering the majority of 3G & 4G devices and the largest fabless semiconductor company in the world. The Graphics team is looking for an Engineer to work on QUALCOMMs Adreno Graphics cores in the area of implementation and methodology. The successful candidate will work in Adreno GPU team and will be responsible for various functions from RTL integration through to physical design. As a member of the Graphics team, the successful applicant will help integrate, implement and develop state of the art GPU cores and will be working closely with the graphics microarchitecture and physical design teams. The successful candidate will possess basic understanding of RTL design and ASIC design flow from RTL to GDS2 such as synthesis, static timing analysis, formal verification, physical design and ECO generation and verification. Knowledge and experience in the following is a definite advantage: * Verilog and System-Verilog languages * RTL integration, partitioning, transformation, and analysis. * Ensure implementation readiness with RTL lint, custom checks, unit level synthesis and clock domain crossing checks. * Package, qualify and deliver FE design collateral. * Develop innovative methods to improve front-end design integration process. * Collaborate effectively with Architecture, Design, DV, SOC, DFT, and IMPL teams spanning multiple sites. * Version control systems * RTL synthesis using physically aware tools * Formal Verification using industry standard tools for RTL-netlist and netlist-netlist checks * ECO methods for functional and timing fixes * Managing design goals in power, performance and area Minimum Skills: * 0-5 years relevant industry experience * Digital design and RTL development understanding using Verilog and/or System Verilog * Basic level knowledge of synthesis, static timing, timing closure, constraints and formal verification * Exposure to Synopsys Design Compiler tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime Preferred Skills: * Experience with UNIX, Perl, TCL or shell scripting * Ability to analyze architectural and micro architectural details to drive design partitioning. * Knowledge of PPA optimization techniques, Power Intent (UPF/CPF), CDC, RDC, synthesis, physical design and STA. * Excellent interpersonal and analytical skills as well as ability to work independently * Highly motivated, excellent team spirit, obsession with deliverable quality and customer oriented Minimum Qualifications: • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations...