Lead Software Engineer - Verification IP Development

Role responsibilities

The role involves designing, developing, verifying, and deploying Verification IP (VIP). The engineer will work in a collaborative environment to implement layered protocols.

Requirements

Candidates need 3-5 years of experience in functional verification and VIP development. Expertise in SystemVerilog/UVM, C/C++, and specific protocols like PCIe and Ethernet is required.

Key skills

Functional Verification, Verification IP (VIP) Development, SystemVerilog, UVM, C++, C, UCIe, PCIe, CXL, Ethernet

Keywords

Software Engineering, Verification IP, SystemVerilog, UVM, C++, C, UCIe, PCIe, CXL, Ethernet, Functional Verification, Electrical Engineering, Electronics Engineering, Layered Protocols