Lead Physcial Design Engineer
๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ญ๐ฎ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฐ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ญ๐ฎ-๐ฐ๐ฑ ๐๐ฃ๐)
Experience: 4+ yrs
Location: Bengaluru
Job Type: Full-time
We are looking for an experiencedย Lead Physical Design Engineerย to drive the implementation of high-performance semiconductor designs from RTL handoff through GDSII while ensuring optimal power, performance, and area (PPA). This role is ideal for professionals with deep expertise inย Physical Design,ย Floor Planning, andย Cadenceย design tools who are passionate about delivering complex SoC and ASIC implementations for advanced technology nodes.
As a Lead Physical Design Engineer, you will collaborate closely with RTL, DFT, STA, Design Verification, and Foundry teams to develop robust physical implementation strategies, optimize chip layouts, and resolve complex design challenges. You will take ownership of the complete physical design flow, mentor engineering teams, and contribute to design methodologies that improve quality, turnaround time, and silicon success. This role offers the opportunity to work on cutting-edge semiconductor products while influencing technical direction and implementation best practices.
Requirements
Key Responsibilities
- Lead end-to-end physical design implementation from netlist through GDSII for complex ASIC and SoC designs.
- Develop and optimizeย floor planningย strategies to achieve power, performance, area (PPA), and manufacturability targets.
- Perform placement, clock tree synthesis (CTS), routing, timing closure, and physical verification usingย Cadenceimplementation tools.
- Collaborate with RTL, DFT, STA, and verification teams to resolve design issues and ensure successful physical implementation.
- Drive timing closure by optimizing setup, hold, signal integrity, congestion, IR drop, electromigration, and power distribution challenges.
- Conduct physical design reviews, identify implementation risks, and recommend design improvements to enhance overall chip quality.
- Support ECO implementation, design optimization, and signoff activities while ensuring adherence to project schedules.
- Work closely with foundry and packaging teams to address manufacturability, reliability, and tape-out requirements.
- Mentor junior engineers, establish physical design best practices, and contribute to methodology improvements and automation initiatives.
- Prepare technical documentation, implementation reports, and project status updates while collaborating with cross-functional stakeholders.
What Makes You a Great Fit
- 4+ years of hands-on experience inย Physical Designย for ASIC or SoC development.
- Strong expertise inย Floor Planning, placement, CTS, routing, timing closure, and physical signoff methodologies.
- Extensive experience withย Cadenceย physical design tools, including Innovus and related implementation solutions.
- Solid understanding of advanced technology nodes, low-power design techniques, clock distribution, congestion analysis, and PPA optimization.
- Experience with STA, IR drop analysis, signal integrity, electromigration, DRC/LVS, and physical verification flows.
- Familiarity with TCL, Perl, Python, or shell scripting for automation and design flow optimization.
- Strong understanding of semiconductor design methodologies, foundry requirements, and tape-out processes.
- Excellent analytical, debugging, and problem-solving skills with the ability to resolve complex implementation challenges.
- Proven ability to lead technical initiatives, mentor engineering teams, and collaborate effectively across cross-functional design organizations.
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline, with a passion for delivering high-quality semiconductor products.