Sr. ASIC Verification Engineer

Back to jobsSr. ASIC Verification EngineerSunnyvale, CAApply About Tensordyne: Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Tensordyne is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment.   About the role: As a senior member of Tensordyne’s ASIC team, you will lead all phases of ASIC verification and will be responsible for the pre-silicon correctness of Tensordyne’s next-generation family of processors for generative AI inference acceleration. This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne’s vertically integrated, generative AI inference acceleration systems for data centers. Responsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks. SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation) Lead verification planning from architecture through tapeout. Develop block-level, sub-system and full-chip verification environment and tests to implement test plans. Establish reusable verification methodologies and frameworks - scale testbenches to subsystem and full chip environments Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances. Triage and debug functional and performance issues with the design-under-test. Drive verification signoff criteria and quality metrics - handle bug tracking, coverage convergence, regression failures. Mentor and technically guide verification engineers helping them through test planning and verification closure. Perform diagnostic and post-silicon validation tests in the lab. Required Qualifications: 4-8 years of ASIC verification experience - having taken multiple chips through the entire cycle of verification and post silicon validation Expert in System Verilog, UVM, Constraint Randomization, Functional Coverage. Experience in C/C++ or System-C Deep understanding of object oriented programming principles, constrained random stimulus, and...