Design and verify analog circuit components for custom SerDes interface IP (e.g. PLL, Clock Distribution, Transmit and Receive Macros). Mixed Signal Validation of blocks to validate calibration functionality end-to-end. Generate timing models for analog interfaces to digital blocks. Simulation, post-layout verification & co-ordination with layout designers and other engineers on the macro. Co-ordinate with designers to ensure behavioral model accuracy. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. MS in Electrical Engineering or PhD in Electrical Engineering. 7+ years with MS EE and 5+ years with PhD in Electrical Engineering. Experience with deep sub-micron nodes and hands on layout optimization experience. Ability to review DV waveforms and debug calibration related issues. Experienced with behavioural modeling (System Verilog, LEC). Post silicon validation. Python, Perl & other scripting languages for post silicon validation. Analog Behavioural Modeling of PLL Components.
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