Physical Design engineers
饾棫饾椀饾椂饾榾 饾椏饾椉饾椆饾棽 饾椂饾榾 饾棾饾椉饾椏 饾椉饾椈饾棽 饾椉饾棾 饾榿饾椀饾棽 饾棯饾棽饾棽饾椄饾棻饾棶饾槅'饾榾 饾棸饾椆饾椂饾棽饾椈饾榿饾榾
饾棪饾棶饾椆饾棶饾椏饾槅 饾椏饾棶饾椈饾棿饾棽: 饾棩饾榾 饾煭饾煵饾煬饾煬饾煬饾煬饾煬 - 饾棩饾榾 饾煴饾煬饾煬饾煬饾煬饾煬饾煬 (饾椂饾棽 饾棞饾棥饾棩 饾煭饾煵-饾煴饾煬 饾棢饾棧饾棓)
Experience: 4+ yrs
Location: Bengaluru
Job Type: Full-time
We are seeking talented聽Physical Design Engineers聽to contribute to the implementation of high-performance ASIC and SoC designs across advanced semiconductor technology nodes. This role is ideal for professionals with strong expertise in聽Cadence聽physical design tools and聽Floorplanning, along with a passion for delivering optimized silicon solutions that meet aggressive power, performance, and area (PPA) goals.
As a Physical Design Engineer, you will work closely with RTL, Design Verification, DFT, STA, and Foundry teams throughout the complete physical implementation cycle. You will be responsible for developing efficient floorplans, driving timing closure, resolving implementation challenges, and ensuring successful tape-outs. This position offers the opportunity to work on cutting-edge semiconductor products while contributing to advanced implementation methodologies and continuous process improvements.
Requirements
Key Responsibilities
- Execute end-to-end physical design implementation from synthesized netlist through GDSII for ASIC and SoC projects.
- Develop and optimize聽floorplanning聽strategies to achieve target PPA while minimizing congestion and improving routability.
- Perform placement, clock tree synthesis (CTS), routing, timing optimization, and physical verification using聽Cadence聽implementation tools.
- Collaborate with RTL, DFT, STA, and Verification teams to resolve design issues and support successful physical implementation.
- Drive timing closure by resolving setup, hold, signal integrity, IR drop, electromigration, and congestion-related challenges.
- Support engineering change orders (ECOs), implementation updates, and design optimization throughout the project lifecycle.
- Perform design quality checks, physical verification, and signoff activities to ensure compliance with foundry and manufacturing requirements.
- Develop automation scripts to improve physical design productivity, reporting, and implementation efficiency.
- Participate in technical design reviews, identify implementation risks, and recommend improvements for better design quality and execution.
- Document implementation methodologies, design flows, and best practices while contributing to continuous process improvement initiatives.
What Makes You a Great Fit
- 4+ years of experience in聽Physical Design聽for ASIC or SoC implementation.
- Strong hands-on expertise with聽Cadence聽physical design tools, including Innovus and associated implementation solutions.
- Solid understanding of聽Floorplanning, placement, CTS, routing, timing closure, and physical signoff methodologies.
- Experience working with advanced semiconductor technology nodes and optimizing designs for power, performance, and area (PPA).
- Good understanding of static timing analysis, signal integrity, IR drop, electromigration, DRC, LVS, and physical verification flows.
- Familiarity with scripting languages such as TCL, Python, Perl, or Shell for automation and design flow optimization.
- Strong analytical, debugging, and problem-solving skills with the ability to resolve complex implementation challenges.
- Excellent collaboration and communication skills with experience working across multidisciplinary semiconductor engineering teams.
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline.
- Passion for semiconductor innovation, continuous learning, and delivering high-quality silicon solutions within challenging project timelines.