HDD Servo Processing Subsystem Architecture Lead

Google Chrome Microsoft Edge Apple Safari Mozilla Firefox HDD Servo Processing Subsystem Architecture LeadFull-timeJob Type (exemption status): Exempt position - Please see related compensation & benefits details belowSalary Range: 215,900.00-287,800.00Business Function: FirmwareWork Location: San Jose Great Oaks Headquarters--LOC_WDT_USCA23Company DescriptionWD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time. That’s where we come in. We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide. This isn’t theoretical work. It’s real systems, at real scale, people solving some of the hardest challenges in technology today. We’re looking for people who want to build, solve, and operate at that level. Join us and let’s shape the future of data.Job DescriptionWe are seeking an experienced HDD Servo Processing Subsystem Architecture Lead to join our organization in San Jose, CA, United States. In this pivotal role, you will drive the strategic vision and execution of the servo real-time compute platform architecture—encompassing firmware architecture, instruction set architecture (ISA), and SoC microarchitecture—to enable next-generation HDD products with multiple concurrent data streams and multi-actuator control. You will be accountable for defining a coherent, scalable platform strategy that balances technical feasibility with economic viability across program schedules, power envelopes, and cost constraints. This position offers the opportunity to shape the future of storage technology while leading cross-functional teams across multiple locations and technical disciplines.ESSENTIAL DUTIES AND RESPONSIBILITIESDefine and maintain a future-state servo real-time compute architecture and ISA that scales from single to multiple concurrent data streams and supports concurrent control of multiple actuators and heads, with explicit guidance to SoC and servo teams on power, area, and performance trade-offsCo-lead SoC microarchitecture decisions affecting servo compute, including core count and placement, memory hierarchy, interconnect design, and dynamic control accelerators, ensuring that FPGA prototype work and accelerator designs map cleanly into production-ready firmware and tools modelsOwn servo compute resource management and budgeting, including instruction/data memory allocation, processor cycle and path-length limits, and regression thresholds; drive adherence through continuous integration practices to prevent late-stage resource conflicts Lead the co-design of firmware platform architecture, including core control-loop implementations, multi-cluster and multi-actuator orchestration, and cross-generation stability, ensuring deterministic real-time performance across multiple SoC generationsDrive evolution of the servo compute tooling ecosystem—including internal compiler, real-time compute platform simulator, Renode-based system simulation, debug and diagnostics tools, and profiling/debug flows—to support multi-cluster, multi-stream characterization and debugging by servo, manufacturing, and validation teamsCoordinate across geographically distributed teams (servo firmware (FW), SoC architecture/design, recording subsystem/algorithms, servo tools, manufacturing FW, and test) to align platform decisions with program risk, schedules, yield, and customer experience objectivesDeliver a major multi-stream and multi-actuator capability that meets control performance and power targets on a new SoC generation, demonstrating the viability of the defined architecture and ISAStrengthen the organizational pipeline by evolving servo compute training, standards, and review processes into a broader...