Software R&D Engineer, RTL Optimization Tools

Role responsibilities

Develop internal EDA tools using C++, parallel computing, and machine learning to optimize RTL quality, timing, and power. The role involves inventing new methods for graph-based RTL traversal and collaborating with design teams to deploy these solutions.

Requirements

Requires an MS or PhD in Electrical Engineering or Computer Science with 3+ years of experience in CAD software and VLSI design. Candidates must be proficient in C++ algorithm development and familiar with RTL design and EDA techniques.

Key skills

C++, RTL Design, Graph Algorithms, VLSI Hardware Design, Logic Synthesis, Verilog, SystemVerilog, Machine Learning, Static Timing Analysis, SAT Solvers, Multithreading, Distributed Computing, DFT, Clock Distribution, Power Gating, SOC Integration

Keywords

RTL, EDA, C++, VLSI, Graph Neural Networks, Large Language Models, Reinforcement Learning, GANs, Verilog, SystemVerilog, Logic Synthesis, Static Timing Analysis, SAT Solvers, DFT, MBIST, Scan Chain Insertion, SOC, IP Integration, Verific, Espresso, Multithreading, Distributed Computing, Combinatorial Optimization, GPU, AI Hardware, Pattern Matching, Clocking, Power Delivery, Data Path Latency