Senior Design Engineer - IP Office

Drive IP selection, qualification, and adoption for AI SoC programs, ensuring alignment with product requirements and SoC landing zones. Lead IP acquisition (through IP license/SOW), release management, quality assurance, and integration of third-party and internal IPs. Establish and scale robust processes for IP release, updates, QA, integration, and pre/post-silicon validation. Track third-party and internal IP releases and updates, ensuring timely release of collaterals to internal SOC teams for integration and issue resolution. Partner with Architecture, Design, Physical Design (PD), Design for Test (DFT), Validation, Packaging and Board Design teams to optimize design tradeoffs and drive integration quality reviews. Drive cross-functional resolution of pre- and post-silicon IP issues and integration challenges. Provide technical leadership through collaboration, influence, and effective stakeholder engagement across engineering organizations and vendors. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience 4+ years of experience in Integration and debug of IPs in major CPU, GPU or AI accelerator SoC's and close interactions with Major IP vendors and suppliers of SoCs 4+ years Design experience either in IP development or in SoC level Integration of at least one of the following areas: SRAM design, Register Files and Memory Compilers High Speed serial and/or Parallel IOs Sub-system and SoC integration Detail understanding of IP collaterals required for front end, physical design and DFT integration into SOC Track record of successful tape outs in deep sub-micron technologies 2+ years of experience in IP office functions of a major CPU, GPU or AI SoC Established reputation in interactions with leading suppliers of IPs in 112G/224G class Ethernet, PCIe 5/6, HBM3/4, temperature, voltage and process monitors Scripting language such as Python or Perl Knowledge of Front-end and back-end IP Integration flows in a SoC Experience working with customers, external IP vendors and silicon foundry This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation.