Principal Memory Controller Architect

Architecting and development of memory controllers Reviewing Memory technology roadmaps including, but not limited to: DDR5, DDR6, LPDDR, HBM, Type 3 CXL-based Memory, RDIMM, MRDIMM, LP-MRDIMM, and emerging memory technologies Working closely with memory controller micro-architects, verification and validation to drive features into production Working with Vendors evaluate IP and make recommendations Work with Performance Modeling team to develop cycle approximate model of the controller and also analyze SOC/platform Azure workload results Working closely with Strategic Planning and Architecture as well as internal customers to understand workload and use case requirements with specific focus on identifying full stack optimization opportunities within the context of the overall memory hierarchy Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 7+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 15+ years technical engineering experience OR equivalent experience. 1+ year(s) experience working on or leading projects from beginning-to-end Delivered Architecture or Design or Verification specs for multiple generations of Memory Controllers Familiar with DDR JEDEC specs Experience in SoC memory hierarchy/architecture, and knowledge of emerging memory technologies.