๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฐ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฑ-๐ฐ๐ฌ ๐๐ฃ๐)
Experience: 2+ yrs
Location: Bengaluru, Karnataka, India, Hyderabad, Telangana, India
Job Type: Full-time
We are looking for a highly motivatedย Physical Design Engineerย to join our semiconductor engineering team and contribute to the implementation and optimization of complex ASIC and SoC designs across advanced technology nodes. This role is ideal for professionals with strong expertise inย Physical Design, Place and Route (PNR), Static Timing Analysis (STA), and EMIR (Electromigration & IR Drop Analysis)ย who are passionate about delivering high-performance, power-efficient, and manufacturable silicon solutions.
As a Physical Design Engineer, you will work closely with RTL, DFT, STA, Signoff, and Verification teams to drive the physical implementation flow from floorplanning through timing closure and final signoff. You will play a key role in optimizing performance, power, and area (PPA), resolving implementation challenges, and ensuring that designs meet timing, signal integrity, power integrity, and reliability requirements. This position offers the opportunity to work on cutting-edge semiconductor technologies while collaborating with cross-functional engineering teams in a fast-paced and innovation-driven environment.
Requirements
Key Responsibilities
- Execute end-to-end physical design activities including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and physical verification.
- Perform Place and Route (PNR) implementation while optimizing performance, power, and area (PPA) targets.
- Conduct Static Timing Analysis (STA) and support timing closure across multiple process, voltage, and temperature (PVT) corners.
- Perform EMIR (Electromigration and IR Drop) analysis and implement corrective actions to ensure power integrity and design reliability.
- Analyze and resolve setup, hold, congestion, signal integrity, and physical design violations.
- Collaborate with RTL, DFT, STA, Signoff, and Verification teams to resolve implementation challenges and improve overall design quality.
- Support engineering change orders (ECOs) and incremental implementation throughout the design lifecycle.
- Execute physical verification checks including DRC, LVS, antenna, and density analysis while ensuring compliance with foundry guidelines.
- Develop and enhance automation scripts using TCL, Python, or Perl to improve physical design productivity and workflow efficiency.
- Participate in design reviews, implementation planning, and signoff activities while contributing to continuous process improvement and engineering best practices.
What Makes You a Great Fit
- 2+ years of hands-on experience inย ASIC/SoC Physical Designย and implementation.
- Strong expertise inย Place and Route (PNR)ย using industry-standard EDA tools such as Cadence Innovus or Synopsys ICC2.
- Solid understanding ofย Static Timing Analysis (STA), timing closure methodologies, and signoff processes.
- Hands-on experience performingย EMIR (Electromigration and IR Drop)ย analysis and implementing power integrity optimizations.
- Good understanding of floorplanning, CTS, routing, physical verification, ECO implementation, and PPA optimization.
- Familiarity with advanced semiconductor technology nodes and modern physical design methodologies.
- Proficiency in scripting languages such as TCL, Python, or Perl for automation and workflow enhancement.
- Strong analytical, debugging, and problem-solving skills with attention to detail.
- Excellent communication and collaboration skills with the ability to work effectively in cross-functional engineering teams.
- A passion for semiconductor design, continuous learning, and delivering high-quality, reliable silicon solutions in a fast-paced engineering environment.