Own and architect the end-to-end silicon signoff CAD flow strategy across parasitic extraction (StarRC/Pegasus), static timing analysis (PrimeTime/Tempus), power integrity and IR-drop analysis (Redhawk-SC/Voltus), and physical verification, ensuring production-quality convergence for advanced-node silicon programs. Drive deep quality improvements across signoff methodologies by establishing best practices, defining quality metrics, and implementing systematic validation frameworks that prevent silicon escapes and reduce re-spins. Collaborate with physical design construction teams and front-end RTL teams to ensure seamless integration between implementation and signoff, driving convergence of timing, power, and physical verification closure across multiple concurrent silicon programs. Grow the signoff engineering team by establishing technical standards, conducting design reviews, and fostering a culture of continuous improvement; serve as the technical authority for signoff decisions and trade-offs across the organization. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Bachelor's degree in Electrical Engineering, Computer Engineering, or related field AND 10+ years of experience in silicon signoff CAD engineering, OR Master's degree AND 8+ years of equivalent experience. 10+ years of hands-on experience with parasitic extraction tools (Synopsys StarRC and/or Cadence Pegasus) and static timing analysis tools (Synopsys PrimeTime and/or Cadence Tempus) in advanced process nodes (5nm and below). 10+ years of familiarity with physical design implementation tools (Synopsys Fusion Compiler and/or Cadence Innovus). Good scripting and automation experience in TCL and Python for developing production signoff flows and infrastructure. Experience leading signoff convergence on multiple concurrent tapeouts at 5nm or below with track record of zero-escape silicon quality. Experience working across both Synopsys and Cadence tool ecosystems with the ability to evaluate competitive solutions and drive best-in-class tool selection decisions. Record of driving technical growth in teams, and establishing reusable flow architectures that scale across multiple silicon programs. Experience working on geographically distributed teams with good collaboration skills; familiarity with cloud-based EDA compute environments and modern CI/CD practices for CAD flow development.
Want jobs like this matched to you?
SimpleCareer scores fresh postings against your résumé so you only see the matches that matter.