๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ญ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ญ๐ฌ-๐ฑ๐ฌ ๐๐ฃ๐)
Experience: 4+ yrs
Location: India
Job Type: Full-time
We are seeking an experiencedย Analog Layout Engineerย to design and implement high-performance analog and mixed-signal layouts for advanced semiconductor technologies. This role is ideal for professionals with strong expertise in full-custom analog layout, physical verification, and layout optimization who are passionate about developing silicon-proven designs for next-generation integrated circuits.
As an Analog Layout Engineer, you will collaborate closely with Analog Design, CAD, Physical Verification, and Process Engineering teams to develop robust, manufacturable layouts that meet stringent performance, reliability, and quality requirements. You will take ownership of layouts from block-level implementation through tape-out while ensuring compliance with advanced process technologies and industry-standard design methodologies.
Requirements
Key Responsibilities
- Design and implement high-quality full-custom analog and mixed-signal layouts for advanced technology nodes.
- Develop optimized layouts using device matching, common-centroid placement, symmetry, interdigitation, shielding, guard rings, and dummy device techniques.
- Perform floorplanning and optimize layouts for area, performance, manufacturability, and long-term reliability.
- Execute physical verification activities including DRC, LVS, ERC, and PEX closure using industry-standard verification tools.
- Collaborate with Analog Design, CAD, Physical Verification, and Process teams to resolve layout challenges and improve design quality.
- Ensure layouts comply with process design rules, reliability guidelines, and foundry requirements.
- Support tape-out activities, layout reviews, and implementation of engineering change requests.
- Debug layout-related issues and recommend improvements that enhance performance and manufacturability.
- Document layout methodologies, maintain design quality standards, and deliver projects within established timelines.
- Contribute to continuous improvement initiatives focused on layout methodologies, automation, and design efficiency.
What Makes You a Great Fit
- 4+ years of hands-on experience inย Analog Layoutย and full-custom analog or mixed-signal IC design.
- Strong expertise withย Cadence Virtuoso Layout XL/GXLย and full-custom layout development.
- Excellent understanding of device matching, common-centroid layout, interdigitation, symmetry, shielding, guard rings, and dummy device implementation.
- Hands-on experience performingย DRC, LVS, ERC, and PEXย closure usingย Calibreย orย Cadence Pegasus.
- Experience working with advanced semiconductor technologies includingย FinFETย and process nodes such asย 16nm, 12nm, 7nm, 5nm, 3nm, or 2nm.
- Strong knowledge of electromigration (EM), IR drop, ESD protection, latch-up prevention, and semiconductor reliability guidelines.
- Proven experience owning layouts from block-level implementation through successful tape-out.
- Exposure to high-performance analog IPs such asย PLL, ADC, DAC, Bandgap, LDO, PMIC, SerDes, Memory, or high-speed interfaces is an added advantage.
- Familiarity with scripting languages such asย SKILL, Python, Perl, or TCL, along with knowledge of EM/IR analysis and advanced layout methodologies, is desirable.
- Strong analytical, debugging, communication, and cross-functional collaboration skills with a commitment to delivering high-quality, silicon-ready designs.