RISCV CPU Design Verification Staff Engineer

Skip to main contentOur CompanyOur BusinessSearch for JobsJoin Talent NetworkFAQsProfileEnglishSign InSingle PositionView All JobsRISCV CPU Design Verification Principal EngineerBangalore, India No longer accepting applications.Job ID3086203As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.Qualcomm is hiring strong DV engineers to verify high performance and low power RISC V based CPUs in Bangalore.Roles and Responsibilitieso  Develop and execute verification plans for units and features of a CPU designo  Use simulation and formal verification methodologies to execute test plans, develop testbench components like checkers, assertions, stimulus generators.o  Work closely with system architects, design team, software teams and Soc team to validate system use cases.o  Work closely with emulation team to enable verification on emulators and FPGA platforms.o  Debug and triage failures in simulation, emulation and/or Silicon.BE/BTech degree in CS/EE with 4+ years’ experience.o Implementation of assembly and C language tests for verifying CPU architecture.o  Experience in C/C++, scripting languages, HDLS like Verilog/System Verilogo  Good Understanding of CPU architectures and CPU micro-architectures. Industry experience with CPU architecture (eg: x86, ARM, MIPS, RISCV, POWER) will be a pluso  Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.Preferred Requirements:o  Strong understanding of power management features in CPUs and CPU based Socs.o  In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitectureo  Experience with advanced verification techniques such as formal and assertions is a pluso  Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus