Senior Silicon Engineer

The candidate for this position will be expected and able to complete the following responsibilities: Own block-level DFT architecture, specifications, and implementation for logic and memory test solutions. Drive DFT timing closure and signoff across Scan, MBIST, LBIST, IJTAG, and in-system test modes. Develop and maintain DFT STA constraints, timing exceptions, and signoff methodologies throughout the design cycle. Ensure robust timing of DFT infrastructure, including test clocks, OCCs, clock muxing, and clock-gating architecture. Analyze and resolve DFT timing issues in complex multi-clock and low-power designs using advanced STA techniques. Develop automation and AI-assisted workflows to improve DFT timing analysis, signoff efficiency, and productivity. Support post-silicon debug by correlating timing analysis with silicon test results and driving root-cause resolution. Provide technical leadership and collaborate across Architecture, Design, Verification, Physical Design, CAD, Manufacturing, and Post-Silicon teams to deliver high-quality silicon. BS, MS, or Ph.D. in Electrical Engineering, or Computer Engineering with over 5 years of experience between the fields of DFT & STA. Knowledge about industry standard practice in Design for Test - ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time. Experience developing Scan architecture & micro-arch specifications as it relates to large SOCs along with scan insertion techniques for IP's like PLL's, IO's & Power circuits. Expert at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Siemens Tessent or Synopsys TestMax. Experience in constraint development & timing closure for DFT modes - includes deep analysis of timing paths to identify key issues through Primetime Static Timing Analysis (STA), Clock-Domain-Crossing (CDC), and Reset-Domain-Crossing (RDC). Ability to automate generation of SDC's and also utilize EDA tool generated SDC's for local consumption. Experience with tools such as Genus or Fusion Compiler at lower process nodes. Proficient in scripting languages (Tcl & Perl), and use of AI to improve work efficiency. Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable. Confident problem solver who thrives under pressure to find new, creative solutions. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.