ASIC RTL Design Engineer

This role is for one of the Weekday's clients

Min Experience: 6+ years

Location: Bengaluru
JobType: full-time

We are looking for an experienced ASIC RTL Design Engineer with 6–10 years of hands-on experience in RTL design, SoC integration, and digital design methodologies. The ideal candidate will have strong expertise in SoC Integration, Reset Domain Crossing (RDC), and SoC Design, along with a solid understanding of RTL development, design verification, and industry-standard design practices.

You will work closely with architecture, verification, physical design, DFT, and system teams to develop robust, scalable, and high-performance SoC designs. This role requires strong analytical and problem-solving skills, attention to design quality, and the ability to contribute across different stages of the ASIC development lifecycle.

Requirements

Key Responsibilities

• Design, develop, and maintain high-quality RTL designs for complex ASIC and SoC products using Verilog/SystemVerilog.
• Own and contribute to SoC integration, including integration of IPs, subsystems, interfaces, clocks, resets, and other system-level components.
• Analyze and resolve Reset Domain Crossing (RDC) issues and ensure robust reset architecture across the SoC.
• Participate in SoC design and micro-architecture activities, translating architectural specifications into efficient and synthesizable RTL.
• Develop RTL modules with a strong focus on functionality, performance, power, area, and design quality.
• Integrate and configure third-party and internally developed IPs into complex SoC environments.
• Review design specifications, interface definitions, block-level architectures, and integration requirements.
• Collaborate with verification teams to define design requirements, identify corner cases, and support functional verification.
• Debug RTL and integration issues using simulation, waveform analysis, lint reports, and other design-quality tools.
• Participate in design reviews, code reviews, and technical discussions to ensure adherence to RTL coding and SoC design standards.
• Work with physical design, DFT, CDC/RDC, and implementation teams to resolve design issues and achieve project milestones.
• Support synthesis, timing, and implementation activities by delivering clean, synthesizable, and implementation-ready RTL.
• Contribute to improving RTL design methodologies, automation, coding guidelines, and design quality processes.

Must-Have Skills

• 6–10 years of experience in ASIC/SoC RTL design and development.
• Strong hands-on experience in SoC Integration and integration of multiple IPs/subsystems.
• Strong understanding of RDC (Reset Domain Crossing) concepts, methodologies, and issue resolution.
• Solid experience in SoC Design, including architecture understanding, block integration, clock/reset structures, and system-level connectivity.
• Excellent proficiency in Verilog/SystemVerilog and RTL coding practices.
• Strong understanding of digital design fundamentals, synchronous/asynchronous logic, finite state machines, and clock/reset architectures.
• Experience working with complex ASIC development flows and cross-functional engineering teams.
• Strong debugging, analytical, and problem-solving skills.

Good-to-Have Skills

• Experience with Lint tools and resolving RTL/design-quality violations.
• Hands-on knowledge of CDC (Clock Domain Crossing) analysis and synchronization techniques.
• Familiarity with synthesis, STA, DFT, physical design, and ASIC implementation flows.
• Experience with scripting languages such as Python, Perl, or Tcl for design-flow automation.
• Exposure to industry-standard EDA tools and methodologies.
• Understanding of low-power design concepts and related SoC methodologies.

Education

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.