Senior Physical Design Engineer

Experience and knowledge on Synthesis, RTL / DFT feedback , Timing Constraints. Responsible for RTL to GDS implementation in Physical Design domain for production flagship projects. Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners. Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach. Demonstrate technical expertise across various domains of Physical Design & Timing Signoff. Lead and manage floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA). Drive end-to-end execution from synthesis through place-and-route for block execution, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification. Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes. Clear communications on project status & planning. Proven track record in mentoring, influencing teams, and driving alignment through clear and effective communication. Analytical and problem-solving skills, complemented by advanced scripting capabilities in Perl, TCL, and Python. SCHIE #CSME #Siliconjobs #CCDO Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. BS/MS in Electrical or Computer Engineering or any related degree Preferred 8+ years of experience in semiconductor design. Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. * Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification. Experience in hierarchical design work, Design Planning and integration with multiple production tape-outs using advanced foundry process nodes. Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification. Own complete PD execution of Critical blocks/Partitions/Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions. Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team as required. Proficient in integration activities and design planning (DP) methodology with hands-on experience. Good understanding of timing constraints (functional & DFT), static timing analysis (STA), and timing-power optimization. Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA). Hands-on experience with clock tree synthesis (CTS) and global clock distribution in complex multi-voltage, multi-clock, multi-domain, and low-power designs. Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate). Skilled in industry-standard EDA tools (Synopsys or Cadence). Mentor engineers on technical aspects. Advanced proficiency in Engineering Change Order (ECO) implementation for power and timing convergence, with solid knowledge of functional and DFT ECO closure methodologies.