Senior Silicon Photonics Engineer

Senior Silicon Photonics Engineer LocationSingaporeEmployment TypeFull timeLocation TypeOn-siteDepartmentEngineeringRole OverviewYou will design high-speed silicon photonic integrated circuits operating at the limits of bandwidth and integration, and take them from concept → tapeout → silicon validation.This role is suitable for strong PhD graduates through early-career engineers (~0–5 years experience) who want to work on real, production-bound systems, not just simulations.Roles & ResponsibilitiesDesign and optimize silicon photonic devices and circuits, including:High-speed modulators (MZI, ring, advanced structures)Photodetectors and receiver building blocksPassive components (couplers, filters, routing)Perform multi-domain simulations (EM, circuit, thermal) to meet targets in:Bandwidth (200G/lane+)Insertion loss, extinction ratio, efficiencyImplement PIC layouts (GDS) using foundry PDKs and support tapeoutsCo-design with electronics and packaging teams for CPO/NPO systems:RF effects, parasitics, signal integrity, and thermal constraintsSupport silicon bring-up and characterization:Correlate measurement vs simulationDrive design iterations and improvementsContribute to design libraries, modeling, and methodology developmentRequirementsEducationPhD in Electrical Engineering, Physics, or related field (silicon photonics or closely related area)Experience0–5 years of relevant experience (including fresh PhD graduates)Technical SkillsExperience in design and simulation of silicon photonic devices or PICsStrong understanding of guided-wave optics and device physicsFamiliarity with tools such as Lumerical, COMSOL, or equivalentImplementation SkillsExposure to PIC layout and tapeout flows (PDK, DRC/LVS)System AwarenessBasic understanding of optical communication systems and/or RF effectsNice to HaveExperience with high-speed devices (>100 GHz bandwidth or equivalent)Exposure to CPO/NPO or optical transceiver architecturesFamiliarity with SiPh + III-V integrationExperience with inverse design / adjoint methods (e.g., Meep)Why Join UsWork on real products at 200G/lane+, not just research prototypesDirect impact on AI infrastructure and hyperscale systemsFast iteration cycles from design → silicon → systemHigh ownership early in your careerComprehensive benefits package including health insuranceCollaborative environment with world-class engineering and R&D teamsApply for this Job