Senior Principal Engineer, Digital IC Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a Digital IC Design Senior Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

Participate in design and development of integrated circuits. Develop ASIC specification and micro-architecture of signal processing and communications algorithms. Perform High speed data path RTL implementation using Verilog, synthesis and backend. Provide Integrate vendor IP and support. Specify and implement digital features of a chip. Perform post-silicon debug and correlation. Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification. Assist in design automation of various aspects of the CAD EDA flow. Mentor junior team members. Wage $214,000.00 - $244,000.00 per year.

What We're Looking For

Bachelor’s or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and five (5) years of experience in the job offered or related occupation.

Experience must include five (5) years with each of the following:

•    Gates digital/mixed-signal IC design at 16nm or smaller technology.
•    Entire design cycle from micro-architecture specification definition, Verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
•    Verilog, System Verilog, Perl, Unix Shell.
•    Both RTL development (block and subsystem level) and gate level verification and debug.
•    Matching DSP block model functionality to RTL’s, synthesis, static timing analysis and functional verification.
•    High-speed DSP physical layer products geared for datacenter applications.
•    Chips bring up and functional validation of the product in the lab.
•    System level modeling, debugging and troubleshooting.
•    Designing 802.3 compliant FEC/PCS blocks for SERDES devices for all datarates.
•    Low power digital design for optical module PHY design using advanced technologies nodes.
•    Completing ASIC flow from micro-architecture to customer deployment.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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