Verification CAD Lead

## Grow with us Silicon IP/SoC Verification CAD Lead, Austin, Texas On-Site Hybrid work schedule This is not a remote work opportunity Are you ready to drive and shape the future of Ericsson Silicon’s methodology and tools? Join our dynamic team within the newly established Frontend CAD department, dedicated to defining methodologies and EDA workflows across our global R&D sites located in Austin, Stockholm, and Lund. About Us: At Ericsson Silicon we are at the forefront of technological innovation, driving advancements in ASIC IP and SoC development. We pride ourselves on fostering a dynamic and inclusive work environment where groundbreaking ideas are turned into reality. We are seeking a seasoned Silicon IP/Verification Methodology Lead to join our team and lead our verification strategy. What You'll Do: As the Silicon IP/Verification Methodology Lead, you will play a critical role in shaping and executing our verification methodology for ASIC IP and SoC development. You will leverage your extensive experience and expertise to drive efficiency, ensure quality, and implement best practices across our verification processes. What You'll Bring: • Deep expertise in ASIC IP/ASIC SoC design, RTL, Verilog, and System Verilog. • Proficiency in front-end tools including Verilog simulators, linters, clock domain crossing checkers. • Familiarity with synthesis, static timing analysis, Design-For-Test (DFT). • Knowledge of System-Verilog assertions, checkers, and advanced design verification techniques ais advantageous. • Proficiency in scripting languages such as Perl and Python. • Extensive understanding of modern design methodologies and techniques. • Experience in coordinating and supporting geographically dispersed engineering teams. • Strong communication and presentation skills. • Self-driven with the ability to manage engineering loads across multiple teams. What You'll Own: • Lead the development and implementation of advanced verification methodologies for ASIC IP and SoC projects. • Oversee the verification lifecycle, from planning and testbench development to execution and closure. • Collaborate with cross-functional teams to define verification requirements and ensure alignment with overall project goals. • Drive the adoption of cutting-edge verification tools and technologies to improve productivity and quality. • Mentor and guide junior verification engineers, fostering a culture of continuous learning and improvement. • Analyze and resolve complex verification issues, ensuring timely delivery of high-quality IP and SoC designs. • Maintain up-to-date knowledge of industry trends and advancements in verification techniques and methodologies. • Develop and implement metrics to measure and improve verification effectiveness and efficiency. • Work closely with the design and architecture teams to identify potential verification challenges and develop strategies to address them ## Join our Team Education & Experience • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. • 15+ years of experience in IP/SoC verification, with a proven track record of successful project deliveries. • Deep understanding of verification methodologies, including UVM, OVM, and formal verification techniques. • Extensive experience with verification tools such as VCS and Xcelium. • Strong programming skills in SystemVerilog, Verilog, and scripting languages (e.g., Python). • Excellent problem-solving skills and the ability to analyze and resolve complex verification issues. • Proven leadership abilities, with experience managing and mentoring verification teams. • Strong communication skills, with the ability to effectively collaborate with cross-functional teams. • A proactive and innovative mindset, with a passion for driving continuous improvement. What happens once you apply? Click Here to find all you need to know about what our typical hiring process...