Senior 112G / 224G SerDes Validation Engineer
<p><strong>About the Role</strong></p><p>We are looking for a <strong>hands-on ETH SerDes Validation Engineer</strong> to lead and execute <strong>112G and next-generation 224G SerDes validation</strong> activities.</p><p>The role involves <strong>deep lab work with Keysight test equipment</strong>, <strong>automation development</strong>, and <strong>direct execution of compliance and characterization tests</strong> according to industry standards.</p><p>This position is ideal for an engineer who combines <strong>strong signal-integrity fundamentals</strong>, <strong>standards expertise</strong>, and <strong>automation-driven validation</strong> in high-speed silicon and system environments.</p><p><br></p><p><strong>Key Responsibilities</strong></p><ul><li>Perform <strong>end-to-end validation</strong> of <strong>112G / 224G SerDes PHYs</strong> at silicon, package, and system levels</li><li>Execute <strong>compliance, characterization, and stress tests</strong> for high-speed serial links</li><li>Operate and configure <strong>Keysight high-speed test equipment</strong>, including:</li><li>BERTs, oscilloscopes, AWGs, jitter sources, channel emulators (variable ISI)</li><li>Develop and maintain <strong>automation frameworks</strong> for SerDes validation:</li><li>Test setup control</li><li>Data collection</li><li>Result analysis and reporting</li><li>Python</li><li>Shell scripts under Ubuntu</li><li>SQL skills for data analysis</li><li>Execute and analyze:</li><li>Eye diagrams, jitter (RJ/DJ/TJ), BER, bathtub curves</li><li>CTLE/DFE behavior</li><li>TX FIR optimization</li><li>Channel loss and margin analysis</li><li>Debug signal-integrity issues across:</li><li>Silicon</li><li>Package</li><li>PCB</li><li>Connectors and cables</li><li>Work according to <strong>industry standards</strong>, including:</li><li>IEEE (112G / 224G PAM4)</li><li>Ethernet (802.3ck / 802.3db and beyond)</li><li>Collaborate closely with:</li><li>Design teams (SerDes / PHY)</li><li>SI/PI engineers</li><li>System and board design teams</li><li>Document test methodologies, results, and recommendations clearly</li></ul><p><br></p><p><strong>Required Qualifications</strong></p><ul><li>B.Sc. or M.Sc. in Electrical Engineering or equivalent</li><li><strong>5+ years of experience</strong> in high-speed SerDes validation or signal-integrity roles</li><li>Hands-on experience with <strong>112G PAM4 SerDes validation</strong></li><li>Strong working knowledge of <strong>Keysight validation platforms</strong> (BERTs, scopes, automation APIs)</li><li>Proven ability to <strong>write automation scripts</strong></li><li>Python</li><li>Shell scripts</li><li>SQL for Data Analysis</li><li>Deep understanding of:</li><li>PAM4 signaling</li><li>Jitter decomposition</li><li>BER and margining techniques</li><li>Channel loss and equalization</li><li>Solid understanding of <strong>high-speed standards</strong> (Ethernet, IEEE, OIF)</li><li>Comfortable working independently in the lab and driving issues to closure</li></ul><p><br></p><p><strong>Preferred Qualifications</strong></p><ul><li>Experience with <strong>224G SerDes validation</strong> or early silicon bring-up</li><li>Familiarity with <strong>Keysight N5991 / 8040 / 8160 / PNA / M8040A platforms</strong></li><li>Experience validating:</li><li>112G / 224G Ethernet</li><li>Experience with compliance test specifications and interoperability testing</li></ul><p><br></p><p><strong>What We Offer</strong></p><ul><li>Work on <strong>cutting-edge 112G / 224G SerDes technologies</strong></li><li>Direct impact on next-generation silicon and systems</li><li>Advanced lab environment with state-of-the-art <strong>Keysight equipment</strong></li><li>Highly technical, expert-level team</li><li>Competitive compensation and benefits</li></ul><p></p>