RFIC AMS Design Verification Engineer

Skip to main contentOur CompanyOur BusinessSearch for JobsJoin Talent NetworkFAQsProfileEnglishSign InSingle PositionView All JobsRFIC AMS Design Verification Sr EngineerBangalore, India No longer accepting applications.Job ID3093567As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.About the RoleWe are looking for a motivated and detail-oriented AMS Design Verification Engineer to join our RFIC verification team. In this role, you will contribute to the functional verification of analog and mixed-signal blocks used in WAN,  6G, 5G , SDR, IoT and GPS radio subsystems, working across Real Number Models, RTL, Gate-Level , Gate-PA Netlists on complex mixed-signal SoCs.ResponsibilitiesVerification Planning & ModelingDevelop a thorough understanding of analog & mixed signal block functionality and translate it into structured verification plansBuild high-level behavioral models using SystemVerilog Real Number Modeling (RNM) and Verilog-AMSTestbench Development & ExecutionDesign and implement UVM/SystemVerilog-based testbenches with self-checking architectures, scoreboards, and functional coverageSet up, run, and debug simulation test cases across RTL, Gate-Level, and Gate-PA NetlistsConfigure and execute AMS co-simulation environments integrating SPICE/Spectre with digital simulatorsDebug & AnalysisPerform in-depth debug of analog and mixed-signal circuits using tools such as Cadence xcelium, Verisium debug, Simvision, and Virtuoso  etcAnalyze simulation results, identify root causes of failures, and collaborate with design engineers to drive closureSupport regression management, bug tracking, and coverage analysis to achieve signoff metricsAutomation & ScriptingDevelop and maintain Python, Shell, and TCL scripts to automate verification workflows, regression pipelines, and reporting tasksCollaboration & Post-SiliconWork closely with Analog, Digital Design, DV, Software and DFT engineers in a fast-paced, tape-out-driven environmentProvide support during post-silicon bring-up and correlation activitiesMinimum QualificationsBachelor’s degree in electrical engineering, Electronics Engineering, Computer Engineering, or a related field (Master’s degree preferred)3 years+ of hands-on experience in mixed-signal or analog-digital verification, or equivalent relevant workPreferred SkillsWorking knowledge of Electrical circuit analysisBasic knowledge of Analog & Digital design fundamentalsBasic knowledge of AMS verification fundamentals.Working knowledge of Verilog, SystemVerilog, UVM — testbench architecture and methodologyWorking knowledge of SV Real Number Modeling (RNM) and/or Verilog-AMS behavioral modelingBasic knowledge of core RF/analog and mixed-signal building blocks, including Synthesizers, Amplifiers, PLLs, LNAs, ADCs, DACs, LDOs, Filters, Clock gen, Mixers etcBasic knowledge of any programming interfaces or communication protocols.Proficiency in Python, TCL, and Shell scripting for verification automation is a plusExperience with Cadence EDA tools (Xcelium, SimVision, Verisum debug, Virtuoso) is a plusExposure to SPICE/Spectre for analog circuit analysis is a plusKeywordsAMS Verification, Mixed-Signal Verification, Functional Verification, RF, Analog , Verilog/SystemVerilog, RNM Behavioral Modeling, UVM, Verilog-AMS, Cadence Tool, 5G, 6G, RFIC, SoC Verification