System Level Test Engineer

The candidate for this position will be expected and able to complete the following responsibilities: As a System Level Test Engineer, the candidate is responsible for system‑level test strategy, execution, and diagnostics for complex CPU, GPU, and accelerator‑based platforms across the high‑volume manufacturing and datacentre deployment lifecycle. As a part of this role, you will be expected to support our team by: Manage high volume manufacturing on OSAT for System Level Testing (SLT). Work on improving stability, test time and yield of System Level Testing at OSAT. Collaborating with team members and partner teams to develop and integrate hardware, firmware, content, automation solution for SLT platform. Generate and leverage correlation, characterization, and performance data to optimize outgoing quality and power/performance. Involve in RMA (Feedback from System/Rack failures) checkout, debug and dispositioning. This includes system level failure triage and debug across silicon, hardware, software as well as identification of test coverage improvement at ATE or SLT socket to plug the RMA gap. Product characterization and correlation for power/performance from system to ATE. Define, guide, and contribute to the development of the software automation infrastructure for SLT and system to tester correlation activities. Developing system level test (SLT) platform, strategy, requirements, tools, methodologies across hardware and software. Programming (C# or Python) knowledge is a must. Management of multiple development activities across a variety of product groups. 5+ years in product / test / manufacturing engineering for advanced silicon (CPU, GPU, AI SoC) Proven experience in system‑level validation and system‑scale testing Hands‑on experience with high‑volume manufacturing, system‑level test, and ATE‑based functional testing Experience with production RMA execution, failure analysis, and dispositioning Understanding of system bring‑up, power, memory, IO, interconnects, and firmware interactions Demonstrated ability to perform cross‑domain root cause analysis and drive issues to closure Experience supporting datacentre‑class systems or large‑scale deployments Familiarity with advanced packaging, chiplet‑based designs, and heterogeneous integration Experience correlating lab, manufacturing, and in‑field failures with strong data analysis background Strong scripting or automation background (Python, C/C++, or equivalent) Strong understanding of computer architecture fundamentals: CPU, Memory, PCIe, BIOS/UEFI, OS Basic knowledge of semiconductor manufacturing and product validation flow. Experience with hardware assembly, PC bring-up, lab equipment, or embedded systems is advantageous. Experience in data analysis, Understanding of yield, quality, or manufacturing metrics. Basic understanding of system-level debug methodologies. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.