Principal Subsystem Design Manager

The AISoC silicon team is seeking a Principal Subsystem Design Manager to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property (IP) and System on Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner. Build, hire, and mentor a team of engineers, supporting their career growth and professional development. Manage a Subsystem design team with focus on architectural and micro-architectural based functions and features. Technically lead one or more Subsystems. Interact with architects to develop micro-architectural specifications and work with DV engineers to execute them. Collaborate across teams on vertical and horizontal reuse of components. Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. Provide technical leadership through mentorship and collaboration. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Equivalent Experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience. 8+ years expertise in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure. 8+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug. 15+ years of relevant experience. 7+ years experience with lead roles across cross-functional / cross-time-zone engineering teams. Lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs Experience in Scripting language such as Python or Perl. Experience with design quality and static checks, DFT implementation and hand off to physical design.