Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : SoC Verification
Good to have skills : NA
Minimum 3 year(s) of experience is required
Educational Qualification : 15 years full time education
Summary:
USB Verification Engineer Hardware Engineering / Connectivity IP
Total Industry Experience Minimum 7 years in hardware/protocol verification roles USB Protocol Experience 3+ years hands-on USB 3.x / USB4 / USB-C verification PHY / Controller Verification Experience verifying USB PHY, host/device/dual-role controllers Compliance & Interoperability USB-IF compliance testing and multi-vendor interoperability validation
Prior Protocol Exposure PCIe, DisplayPort, Thunderbolt, or MIPI background advantageous
As a Functional Verification Engineer, a typical day involves developing and implementing comprehensive testbenches to ensure the functional accuracy of digital designs at both block and system levels. The role includes designing various types of tests, such as constrained-random, directed, and coverage-driven, to thoroughly validate the design. Collaboration with design and architecture teams is essential to identify potential edge cases and guarantee exhaustive functional coverage prior to tape-out. This position requires a proactive approach to problem-solving and continuous communication within the team to maintain high-quality verification standards throughout the project lifecycle.
Roles & Responsibilities:
Technical Skills & Competencies
USB Protocol & Standards Knowledge
- Deep understanding of USB 2.0 (HS/FS/LS), USB 3.2 Gen1/Gen2, USB4 v1/v2 specifications
- Strong knowledge of USB-C connector, Alt Mode (DisplayPort, Thunderbolt), and Power Delivery (USB PD 3.1)
- Familiarity with USB host, device, and dual-role port (DRP) / OTG operation
- Understanding of USB protocol layers: physical, link, protocol, and application
- Knowledge of USB tunnelling over USB4 (PCIe, DisplayPort, USB 3.2 tunnels)
Verification Methodologies & Simulation
- Proficient in UVM (Universal Verification Methodology) for USB PHY and controller IP verification
- Experience writing SystemVerilog/VHDL testbenches, sequences, and functional coverage models
- Assertion-based verification (SVA) for protocol compliance checking
- Simulation tool experience: Synopsys VCS, Cadence Xcelium, Mentor Questa
- Experience with USB VIP (Verification IP) from Synopsys, Cadence, or Aldec
- Regression infrastructure management and coverage closure methodologies
Validation & Lab Skills
- Post-silicon USB bring-up, enumeration debug, and link training validation
- USB protocol analyser usage: Ellisys, Teledyne LeCroy, Total Phase
- Signal integrity validation: eye diagram analysis, jitter measurement, LFPS signalling
- USB-IF Compliance Test Specification (CTS) execution for USB 2.0, 3.x, and USB4
- Interoperability testing across host controllers, hubs, and USB peripheral devices
- USB Power Delivery policy engine validation and PD compliance testing
Tools & Scripting
- Python or Perl scripting for test automation, log parsing, and results reporting
- Familiarity with version control systems: Git, Perforce
- Experience with EDA tools: Synopsys VC Verification, Cadence Incisive/Xcelium
- SPICE / AMS simulation exposure for USB PHY signal integrity analysis desirable
Professional & Technical Skills:
- Develop and execute USB verification plans covering functional, protocol compliance, and performance testing
- Build and maintain UVM-based testbenches for USB PHY, host controller, and device controller IP
- Lead post-silicon USB bring-up, enumeration validation, and link training debug
- Execute USB-IF Compliance Test Specifications (CTS) for USB 2.0, USB 3.x, USB4, and USB PD
- Perform signal integrity analysis and correlate simulation results with lab oscilloscope and analyser measurements
- Drive interoperability testing with third-party USB hosts, hubs, and peripheral devices
- Develop automated regression suites and drive functional coverage closure
- Debug and root-cause USB failures across simulation, emulation, and silicon environments
- Collaborate with RTL designers and firmware engineers to resolve protocol and enumeration issues
- Produce detailed test plans, verification closure reports, and USB-IF sign-off documentation
- Provide technical mentorship and code review for junior verification engineers
Additional Information:
- The candidate should have minimum 3 years of experience in SoC Verification.
- This position is based at our Bengaluru office.
- A 15 years full time education is required.
15 years full time education
About Accenture
Accenture is a leading global professional services company that helps the world’s leading businesses, governments and other organizations build their digital core, optimize their operations, accelerate revenue growth and enhance citizen services—creating tangible value at speed and scale. We are a talent- and innovation-led company with approximately 791,000 people serving clients in more than 120 countries. Technology is at the core of change today, and we are one of the world’s leaders in helping drive that change, with strong ecosystem relationships. We combine our strength in technology and leadership in cloud, data and AI with unmatched industry experience, functional expertise and global delivery capability. Our broad range of services, solutions and assets across Strategy & Consulting, Technology, Operations, Industry X and Song, together with our culture of shared success and commitment to creating 360° value, enable us to help our clients reinvent and build trusted, lasting relationships. We measure our success by the 360° value we create for our clients, each other, our shareholders, partners and communities.Visit us at www.accenture.com
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