Server CPU Physical Design Engineer, Senior/Staff level - Cambridge, UK

## Company: Qualcomm Technologies International Ltd ## Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Job Overview Qualcomm is seeking talented Physical Design Engineers to join the Nuvia CPU team in Cambridge, UK. The team is developing next-generation, high-performance, power-efficient custom CPU cores for advanced compute and server-class platforms that will help transform the industry. This is an opportunity to work with some of the most talented and passionate engineers in the world to create CPU designs that push the limits of performance, energy efficiency, and scalability. You will collaborate with global teams across CPU architecture, RTL design, circuit design, CAD, SoC integration, timing, power, and post-silicon validation. This position is open from Senior Engineer through Staff Engineer level, with responsibilities, ownership, and technical leadership scaled according to experience. Key Responsibilities will include As a Server CPU Physical Design Engineer, you will: * Own or contribute to CPU block implementation from RTL/netlist to GDS, including synthesis, floorplanning, power planning, placement, clock tree synthesis, routing, optimization, ECOs, and signoff. * Drive timing closure and physical implementation convergence across multiple modes, corners, and operating conditions. * Work on high-performance, low-power CPU designs with demanding performance, power, and area targets. * Debug and resolve complex implementation issues related to timing, congestion, clocking, routing, IR drop, power integrity, EM, ECO closure, DRC/LVS, and physical verification. * Collaborate closely with RTL, architecture, circuits, CAD, SoC, and post-silicon teams to improve design quality, implementation efficiency, and product performance. * Evaluate and contribute to the design process from concept through productization, including architecture definition, feasibility analysis, pre-silicon design and verification, and post-silicon validation. * Develop and enhance physical design flows, automation, and methodologies to improve productivity and quality of results. * Use data-driven analysis to identify implementation bottlenecks, improve design convergence, and push PPA beyond standard targets. * For Staff-level candidates, provide technical leadership, mentor engineers, define implementation strategies, and drive closure of critical CPU blocks or methodology initiatives. Required Skills and Experience We are looking for candidates with experience in one or more areas of CPU, ASIC, or high-performance digital physical design. The ideal candidate will have: * Strong experience in physical design implementation, including synthesis, floorplanning, placement, CTS, routing, timing closure, ECOs, and signoff. * Strong understanding of static timing analysis and timing closure methodologies, including trade-offs between timing, power, area, congestion, and routability. * Knowledge of high-performance and low-power implementation techniques. * Hands-on experience with industry-standard EDA tools for synthesis, place and route, STA, power analysis, physical verification, and signoff, such as Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, Conformal, or equivalent tools. * Ability to debug complex physical design issues across timing, congestion, clocking, routing, power, and verification domains. * Scripting and automation experience using one or more of TCL, Python, or Perl. * Strong communication skills and the ability to work effectively in a global, cross-functional engineering environment. Minimum Qualifications Candidates should typically have one of the following: * Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in ASIC, CPU, or physical design implementation. OR * Master’s degree in Electrical Engineering, Computer Engineering, Computer...