Systems and Test Integration Engineer - FPGA Integration & Verification

Basic Qualifications

Bachelor's degree in Systems Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience.

 

CLEARANCE REQUIREMENTS:

Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

Job Description

 

ROLE AND POSITION OBJECTIVES:

As a Systems and Test Integration Engineer - FPGA Integration & Verification, on the GDMS TIDES team, you will do two related kinds of FPGA work that support spacecraft payload development. You will design FPGAs from architecture through implementation for the shared test infrastructure. These are FPGAs that handle interface bridging between the test equipment and the unit-under-test, real-time functions like packet timestamping and precision command scheduling, and other test-support work. You will also bring up FPGA interfaces on real hardware, maturing the development platform and enabling test software infrastructure to be built. This is FPGA engineering for the Hardware Development Environment (HDE), a shared engineering platform that all spacecraft payload programs at GDMS build on.

In this role you will own FPGA features end to end, from microarchitecture through lab bring-up, and grow toward independently architecting test FPGAs. Your work directly enables faster hardware bring-up, more reliable integration testing, and a smoother path from development to design verification to flight readiness. You will contribute to FPGA architecture decisions, write RTL, establish interface communications in the lab, and help shape how the HDE evolves, all in a mission-focused environment.

Preferred Skills & Experience:

• 3+ years of experience in FPGA design, integration, and hardware bring-up, spanning microarchitecture definition through hardware integration
• Proficiency in SystemVerilog and/or VHDL for RTL design
• Comfortable writing designer-level testbenches to stimulate and validate your own submodules in simulation before hardware
• Ability to work at the systems level: understanding how the surrounding system drives test FPGA requirements and how the test FPGA fits into the larger test-and-integration picture
• Hands-on experience designing and integrating FPGA interfaces such as Ethernet, JESD204B/C, SPI, etc.
• Proficiency in synchronous and asynchronous design principles, timing closure, and constraint generation
• Experience with FPGA vendor toolchains (Xilinx/AMD Vivado, Lattice Diamond/Radiant, or equivalent)
• Hands-on experience integrating FPGA interfaces in a lab environment (JTAG, oscilloscopes, protocol analyzers, debugging on real hardware)
• Proficiency in scripting languages such as Linux shell scripts, Python, and Tcl
• Experience with Git-based version control workflows (branching strategies, merge requests, code review)
• Experience working in Linux environments (RHEL, Ubuntu); comfortable at the command line
• Familiarity with CI/CD platforms (GitLab CI or equivalent) for FPGA build and release automation
• Experience with computer networking (Ethernet configuration, subnets, routing)
• Familiarity with agile/scrum workflows and sprint-based delivery
• Experience deriving test FPGA requirements from system-level needs: working with hardware, systems, and test engineers to define what a test FPGA has to do, not just implementing a fully-architected design

Key Responsibilities

• Design FPGAs for the shared test infrastructure, including interface translation between the unit under test and the test system, and real-time functions like packet timestamping and precision command scheduling
• Integrate and debug FPGA communication interfaces on real hardware
• Build and maintain CI/CD stages that produce FPGA artifacts to be used by the shared development environment (Python packages, versioned images, published binaries)
• Collaborate with the test software and test hardware groups to define interfaces, coordinate integration, and align on platform capabilities
• Contribute to the platform's evolution across versions as the HDE grows toward full flight-representative capability
• Debug firmware issues using lab instrumentation, waveform capture, and structured investigation
• Document FPGA designs, bring-up procedures, and integration approaches

What Sets You Apart

• You prefer to see the whole system. You see how the FPGA, the surrounding hardware, and the test infrastructure connect, and you use that view to drive design decisions
• You enjoy the mix of FPGA design work and hands-on hardware bring-up. You'd rather split your time between HDL and the lab than do only one or the other
• You write clean, maintainable RTL and scripts that others can extend
• You take ownership of complex integration problems, from microarchitecture through lab bring-up, and drive them to closure
• You're comfortable in the lab. You know how to isolate whether a problem is in the HDL, the board, the cable, or the instrument, and you don't stop until you know
• Exposure to verification methodologies like the Universal Verification Methodology (UVM) is a plus
• You communicate clearly with hardware, systems, and software engineers, translating between disciplines when needed
• You identify opportunities to apply AI tools for continuous improvement and automation

Our Commitment to You:

• An exciting career path with opportunities for continuous learning and development.
• Research oriented work, alongside award winning teams developing practical solutions for our nation’s security
• Flexible schedules with every other Friday off work, if desired (9/80 schedule)
• Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more
• See more at gdmissionsystems.com/careers/why-work-for-us/benefits

 

Workplace Options:This position is Facility 100%, Flex

While on-site, you will be a part of the Scottsdale, AZ location

 

Salary Note

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Combined Salary Range

USD $90,833.00 - USD $100,767.00 /Yr.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans