Senior/Staff Digital Design Engineer

Senior/Staff Digital Design Engineer LocationAustin, TX; Bristol, UKEmployment TypeFull timeLocation TypeOn-siteDepartmentEngineeringASICCompensationAustinStarting from $194KBristolStarting from £123KAbout OLIXAI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.The RoleWe are seeking highly skilled and motivated Senior/Staff Digital Design Engineers with a strong focus on CMOS digital design to take end-to-end ownership of high-speed, real-time data-processing silicon, from early algorithm modelling to verified RTL and silicon bring-up. You will join a multidisciplinary group creating next-generation hardware where digital, optical and mixed-signal domains intersect. The ideal candidate will have a strong background in electrical engineering and semiconductor physics, along with a passion for developing reliable, high-performance digital circuits that drive breakthrough AI hardware.ResponsibilitiesArchitect, design and implement high‑throughput digital pipelines (multi‑GSPS input rate, continuous streaming data paths, deep pipelining and hand‑shaking) in advanced CMOS nodesPrototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring‑up real‑time demos, exercise high‑speed transceivers, and feed learnings back into the ASICModel algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‑level sign‑offOwn RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static‑timing closure, formal and constrained‑random verificationAnalyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth‑per‑watt targetsCollaborate with optical‑hardware, mixed‑signal and software teams to optimise data‑converter interfaces, clock‑domain crossings and firmware abstractionsMentor junior engineers, lead design reviews and champion best‑practice design methodologiesSkills & Experience7+ years of hands‑on digital design for high‑performance ASICs or SoCs, including ownership of at least one product that processes a continuous real‑time data streamProven success closing timing on multi‑hundred‑MHz to multi‑GHz clock domains and integrating high‑speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar)Expertise with industry‑standard EDA flows: RTL synthesis, CDC/RDC, STA, power‑intent (UPF/CPF), lint, and gate‑level simulationDemonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the labProficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed‑point analysis and test‑vector generationSolid grounding in digital signal‑processing concepts, computer‑architecture fundamentals and semiconductor device physicsExcellent communication and cross‑functional collaboration abilities; thrives in a fast‑moving, ambiguous environmentNice to haveTape‑out experience at 22 nm or belowKnowledge of coherent optical links or photonic‑electronic co‑design.Familiarity with AI/ML workloads, systolic arrays or tensor‑processing architectures.Contributions to open‑source RTL, verification frameworks or FPGA boards.Compensation & EquityCompetitive Salary: Commensurate with your experience, skills, and locationEquity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of itProximity Bonus: We value your time....